Our Services

Deep Learning

Convolutional, Auto-Encoders and RNNs with applications in computer vision and radar signal processing: Semantic segmentation, pose estimation, key-point detection, target detection, classification and tracking, sensor signal processing and sensor fusion.

Computer vision

Image and video segmentation, target classification and tracking in image coordinates and in world coordinates, video based vital signs estimator, 3D reconstruction for multiple views, stereo-vision, deep learning for stereo vision and 3D reconstruction from a single image, visual odometry, real time camera calibration for autonomous vehicles and more. 

RADAR/LIDAR vision and signal processing

Entire pipeline from detection to tracking and classification including range and Doppler estimation, DOA estimation, super-resolution methods in DOA, range and Doppler, tracking, Kalman filtering (EKF+variants),RNN based filtering, target classification and discrimination using temporal/spectral and spatial signatures. Applications include: remote sensing of vital signs, drone detection and classification, signs of life detection in fires, through wall imaging and classification and more. 

Communications

Signal detection and synchronization, digital correction of the front end impairments, digital pre-distortion, PAPR reduction methods, distorted signal recovery,  MIMO processing, as well as reverse engineering of communications protocols based on air-recordings on downlink/uplink. Communications standards including 802.11 (Wi-Fi and Wigig) and 5G.

Chip/FPGA design

  • Architecture design: Full SoC architecture that include algorithm design, simulation and implementation, design for power, performance and area optimization based on target process or FPGA and floor planning

  • RTL Design and Verification 

  • DFT: Architecture design, Scan and MBIST insertion and ATPG, JTAG boundary scan, memory repair considerations in advanced processes as well as memory ECC design – Doing all this with deep consideration for the functionality of the circtuit, timing closure, area and power. 

  • RTL to GDS: Timing constraints design and verification, physical synthesis, place and route, timing closure and sign-off, chip finishing and layout verification. 

  • RTL to FPGA GateWare: Timing constraints design and verification, Synthesis and Place and Route, timing closure. 

  • Project/Program management for all technology projects:

    • IP selection and vendor management and agreement negotiations. 

    • Tool flow selection and bring up including vendor selection and negotiations. 

    • Foundry relations and process selection.

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