Our Services

RADAR/LIDAR vision and signal processing

Entire pipeline from detection to tracking and classification including range and Doppler estimation, DOA estimation, super-resolution methods in DOA, range and Doppler, tracking, Kalman filtering (EKF+variants),RNN based filtering, target classification and discrimination using temporal/spectral and spatial signatures. Applications include: remote sensing of vital signs, drone detection and classification, signs of life detection in fires, through wall imaging and classification and more. 

Computer vision

Image and video segmentation, target classification and tracking in image coordinates and in world coordinates, video based vital signs estimator, 3D reconstruction for multiple views, stereo-vision, deep learning for stereo vision and 3D reconstruction from a single image, visual odometry, real time camera calibration for autonomous vehicles and more. 

CUDA realtime implementation

Achieving optimal performance for real-time algorithms running on GPUs goes far beyond just knowing the Cuda or OpenCL library usage. Different algorithm architectures require specialized tuning, memory access optimization, hidden latencies to consider, etc.


We are experienced with working in many domains and can design algorithms from concept to real-time deployment on GPUs, as well as taking existing algorithms and porting them to Cuda on GPUs or other embedded platforms.

We have experience in many different algorithmic domains ranging from Radar signal processing, wireless and wired communication signals processing, computer vision, machine learning, deep learning, electromagnetics, linear algebra, pattern recognition


If you have an existing CPU based on non-real time algorithms that need GPU speed up, we do: code analysis and profiling, CPU to GPU code optimization and porting, multi-GPU support and more. We have deep expertise in CUDA and OpenCL for both porting existing prototyped systems and algorithms to designing from scratch.

Antennas Design and Electromagnetic Simulations

  • Custom antennas development up to 130 GHz, antenna arrays for radars and sensors, IoT antennas and Integrated antennas. Antennas on-chip and, antennas-on-package. EM Modelling and simulations, far-field and near-field antennas testing and characterization, EM analysis of existing antennas and PCB products. Radome Impact simulation on antenna performance.

  • Phased array overall concept development including functionality and specifications. Arrays system calculations and system optimization. Link budget calculations. Front End (FE) SoC architecture and functional block diagram development. Antenna array development and development support. Beamforming systems analysis.

  • RF Board Design up to 30 GHz including System definitions and line up analysis, schematic level, and EM design, layout, prototype bring-up, testing, and full characterization inc. array calibration.  Discrete components design LNAs, Power Amplifiers (GaN), up/down converters, synthesizers, rectifiers, filters, phase-shifter, attenuators, mixers.  Existing designs schematic and layout review and optimization. Existing product testing.

Deep Learning

Convolutional, Auto-Encoders and RNNs with applications in computer vision and radar signal processing: Semantic segmentation, pose estimation, key-point detection, target detection, classification and tracking, sensor signal processing and sensor fusion.


Signal detection and synchronization, digital correction of the front end impairments, digital pre-distortion, PAPR reduction methods, distorted signal recovery,  MIMO processing, as well as reverse engineering of communications protocols based on air-recordings on downlink/uplink. Communications standards including 802.11 (Wi-Fi and Wigig) and 5G.

Chip/FPGA design

  • RTL to GDS implementation: Timing constraints design and verification, physical synthesis, place and route, timing closure for high frequencies >1Ghz and sign-off, chip finishing and layout verification. Many successful tapeouts in cutting edge process technologies such as 7nm FF+, 12nm, 16nm, 28nm in TSMC and 14nm GF, and Intel processes as well. Many chip sizes from small to 700MM^2 (max reticle size).

  • Architecture design: Full SoC architecture and uArchitecture, that includes algorithm design, simulation, implementation, design for power, performance and area optimization based on target process and floor plan.

  • RTL Design and UVM constrained-random Verification 

  • DFT: Architecture design, Scan and MBIST insertion and ATPG, JTAG boundary scan, memory repair considerations in advanced processes as well as memory ECC design – Doing all this with deep consideration for the functionality of the circuit, timing closure, area and power. 

  • RTL to FPGA GateWare: Timing constraints design and verification, Synthesis and Place and Route, timing closure. 

  • Project/Program management for all technology projects:

    • IP selection and vendor management and agreement negotiations. 

    • Tool flow selection and bring up including vendor selection and negotiations. 

    • Foundry relations and process selection.

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