High level introduction to ASIC design
Updated: May 8, 2019
Some claim that designing chips, or ASICs (Application Specific Integrated Circuits) is an art form bordering on black magic. While for those not skilled in the art, it might appear that way, for those experts who are highly skilled in the craft, it is nothing more than a very well defined and well rehearsed, although very complicated, process that takes you from an idea, to a functional working chip that you can ship and sell to your customers.
This is an attempt at introducing this art form to those who are wondering how an ASIC chip is designed, but are outside this incredible and costly world of chip design.
An ASIC stands for Application Specific Integrated Circuit, which in simple words means: an integrated circuit, which is a big circuit that performs a specific function or functions and is integrated into a silicon chip. An SoC stands for a system-on-a-chip which means an entire system that might include many types of functionality that used to be performed by many chips is now crammed onto a single chip. For example, a cellular baseband processor chip like everybody has inside their cell phones is an ASIC SoC designed to perform voice and data mobile communications. ASIC Design, or IC Design, or chip design, are all different terms to describe the sequence of steps of taking an idea or a concept, and going through the process of designing millions of small electronic circuits that go inside, a silicon chip, that performs the functions that the concept or idea called for.
The invention of the transistor and the subsequent ability to consistently minimize (shrink) its size, made it possible to cram the functionality equivalent of 200,000 Figure-1 rooms into a small chip as shown in Figure-2 below.
How the ASIC chip is designed
1. Architecture Design. In this stage, the designers are specifying at a high level what functionality they would like the chip to perform. Later on, this functionality or architecture document will be used to derive a more low-level architecture called micro-architecture, where every function will be broken down into sub-functions and sub-building blocks. You can think of it as building a house, first, you draw the high-level architecture, shapes, window and door locations, etc, and later you plan for plumbing, electricity, etc based on the high-level architecture and where everything is located. This stage is heavily influenced by marketing obviously since a lot of the features or functionality is requested or vetted by the customers.
2. Choosing the manufacturing technology (or the process node). In this stage, the ASIC team needs to decide which silicon manufacturing technology it will target during the design process. This is a critical decision that takes into account many factors such as: a) IP (Intellectual Property) availability. What building blocks does the designer have to work within this process node? Going back to our house example, what pre-fab windows, doors, cabinets, etc. can I choose from to quickly and with high quality build my house. b) Price. The more advanced the node, the more expensive it is, but the smaller the silicon chip will be. I.e., if the volume of your product is significant (10’s of millions a year), you might gain from going with a smaller node. c) The complexity of the design. The more advanced the node, the more complex and time consuming it is to design into it.
3. HDL Implementation. HDL stands for Hardware Description Language. Which is basically a language that is used to describe hardware at a high level. The most commonly used languages for this are Verilog System-Verilog and VHDL. Hardware designers, AKA logic designers, basically program in these languages but the result (after a process called synthesis), is hardware circuits, rather than software. These high-level languages allow designers to quickly describe very large amounts of hardware (or logic), with very little code, which helps readability as well as verification and debug.
4. Synthesis. A set of software tools controlled by engineers that read in the HDL and other relevant inputs and produces a circuit description composed of standard components like gates (AND, NAND, OR, NOR, etc.) that implements the functionality described by the designer in the HDL.
5. Logic Verification. This is a process by which the HDL or the hardware description is verified against the specifications. This is one of the most critical and time-consuming processes in chip design. A lot of standards and non-standard verification methodologies came and went, and some are still dominant in the market. Choosing the right set of methodologies for your project is a delicate trade-off between schedule (100% verification takes infinite time), and quality, you need to be very confident that the chip you’re taping-out (i.e., send to production) is going to come back working.
6. Place & Route - a semi-automatic process done by engineers and other software tools, by which the physical connectivity and placement (i.e., layout) of each every cell in the chip is done.
7. Physical Verification. Verifying that the physical layout does not violate the fab’s design rules. If it does, that can cause chips that don’t work, yield issues, and more.
8. Tape-out. After all the previous stages are done and signed-off by the team, you are ready for tape-out, and you send out the full chip database to the fab for fabrication.
About the Author:
Guy Regev is a co-founder and Managing Partner of AlephZero Consulting. He is a veteran of the IC design Industry, with over 20 years of both management and hand-on expertise across all technical disciplines of chip and FPGA design. Extensive experience managing cross-functional HW/SW/FW international projects as well as hands-on experience through all aspects of the chip design/FPGA and productizing, with a proven track record of successful, time-crunched tape-outs and market intros of flagship products. He is also an Expert Witness for cases that involve hardware, chip, IC Design, SoC Design or FPGA design, as well as EDA tools, software, and embedded firmware. More about him at: https://www.guyregev.com/