Guy RegevJan 223 minAsynchronous RESET timing-closure - hell or heaven? (Part I)In large SoCs (system-on-a-chip) or relatively slow FPGAs properly distributing the asynchronous reset lines to all the flops is a relati...
Guy RegevAug 15, 20192 minunderstanding overfittingOverfitting is a frequently used term in the data science community; yet the most common explanation or “definition” that I hear regardin...
Guy RegevMay 29, 20193 minMIMO-Radar Signal Processing ChaiNIn this paper we provide a short overview of a modern MIMO radar system.
Guy RegevMay 9, 20191 minOn The Sensitivity of direction of arrival (DOA) Estimation to Baseline InaccuraciesThe following paper shows the sensitivity of DOA algorithms to the array baseline length. It is shown that a minor error (1.8mm @5GHz) can..
Guy RegevMay 7, 20194 minHigh level introduction to ASIC designSome claim that designing chips, or ASICs (Application Specific Integrated Circuits) is an art form bordering on black magic.
Guy RegevMay 1, 20193 minOn Direction of Arrival Estimation with 1-bit Quantizer (Radar SIgnal Processing)Ilia Yoffe 1,2 ilia@alephzero.ai Nir Regev 1,2 nir@alephzero.ai Dov Wulich 1 1 EE Dept., Ben-Gurion University of the Negev, Beer-Sheva, ...
Guy RegevMay 1, 20197 minReduction in ATE Test time for Core Wrapped blocks by Avoiding Q->SI atspeed timing Sreenath Mandagani Guy Regev CSIG/NPG/CID/Wireless Access, Intel December, 2016 What is the problem being solved by this work, or future ...
Guy RegevMay 1, 201912 minA Methodology for Timely Verification of a Complex SoC/CHIPThis paper presents a novel and alternative methodology of logic or functional verification of a system-on-a-chip integrated- circuit. Th...
