Blog | alephzero-consulting

Asynchronous RESET timing-closure - hell or heaven? (Part I)

In large SoCs (system-on-a-chip) or relatively slow FPGAs properly distributing the asynchronous reset lines to all the flops is a...

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understanding overfitting

Overfitting is a frequently used term in the data science community; yet the most common explanation or “definition” that I hear...

MIMO-Radar Signal Processing ChaiN

In this paper we provide a short overview of a modern MIMO radar system.

On The Sensitivity of direction of arrival (DOA) Estimation to Baseline Inaccuracies

The following paper shows the sensitivity of DOA algorithms to the array baseline length. It is shown that a minor error (1.8mm @5GHz) can..

High level introduction to ASIC design

Some claim that designing chips, or ASICs (Application Specific Integrated Circuits) is an art form bordering on black magic.

On Direction of Arrival Estimation with 1-bit Quantizer (Radar SIgnal Processing)

Ilia Yoffe 1,2 ilia@alephzero.ai Nir Regev 1,2 nir@alephzero.ai Dov Wulich 1 1 EE Dept., Ben-Gurion University of the Negev, Beer-Sheva,...

Reduction in ATE Test time for Core Wrapped blocks by Avoiding Q->SI atspeed timing

Sreenath Mandagani Guy Regev CSIG/NPG/CID/Wireless Access, Intel December, 2016 What is the problem being solved by this work, or future...

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A Methodology for Timely Verification of a Complex SoC/CHIP

This paper presents a novel and alternative methodology of logic or functional verification of a system-on-a-chip integrated- circuit....